I was going over the schematic the other night and was wondering to my self what the total signal reduction is at the JFET divider stage. What we have is a basic voltage divider circuit with a JFET as part of the variable resistance.
When the JFET is totally "ON" there will be a very small Drain-Source resistance (RDS On) between the 27k resistor and the 10k resistor. For simplicity, let's assume it's ideal and RDS On = 0 ohms. Then we have:
Remember, this is only the loss of the JFET stage. This does not include any loss from the input transformer or the input attenuator.
I will run some actual tests and compare the results soon. Stay tuned !