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I was going over the schematic the other night and was wondering to my self what the total signal reduction is at the JFET divider stage. What we have is a basic voltage divider circuit with a JFET as part of the variable resistance.

When the JFET is totally "ON" there will be a very small Drain-Source resistance (RDS On) between the 27k resistor and the 10k resistor. For simplicity, let's assume it's ideal and RDS On = 0 ohms. Then we have:
At this point we can calculate the total signal reduction for the JFET Divider stage:

Total signal loss is almost -11.5db. A SPICE simulation calculates the loss to be:

This is the total signal reduction that can be expected from the JFET Divider stage.
Remember, this is only the loss of the JFET stage. This does not include any loss from the input transformer or the input attenuator.

I will run some actual tests and compare the results soon. Stay tuned !

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