The gain reduction stage of an 1176 is made up of two phase inverting amplifiers followed by rectifying diodes. The circuit is shown here as simulated. The 47k resistor in the feedback loop, near the bottom of the schematic, helps keep the overall circuit gain within usable limits.
Another common emitter stage follows the first one. This stage feeds the upper rectifying diode through the other 6.8uF cap.
Notice that the second stage is padded down with a182k resistor. Not only does this provide DC coupling and bias for the next stage, but it also reduces the signal level to the second stage. Without this pad, the second stage would over amplify the signal beyond what the feedback could correct.
The rectified output signal calculated by SPICE is shown next. This signal is for both Attack and Release controls at their fastest settings. Notice that the signal starts at -4VDC and goes up towards 0V. I added a negative bias (not shown in the schematic) to help model real world results. During the time when the rectified output is equal to 0V the JFET would be fully "ON" in this example and maximum signal reduction would be happening. This of course is assuming that -4V is the required bias voltage for the JFET during normal operation. We shall test that really soon....
I will measure my clone 1176 and take oscilloscope pictures to compare real world gain reduction stage performance with simulation very soon. Stay tuned!